The present invention relates to a multi-phase clock generation circuit for generating a multi-phase clock and, more particularly, to a multi-phase clock generation circuit for generating a multi-phase clock signal by frequency-dividing a clock signal.
Recently, with the proliferation of the Internet and various kinds of communication networks, the traffic has tremendously increased. In order to cope with an enormous information amount, communication devices such as routers and servers which process such information are required to make High-speed interconnection between semiconductor elements, semiconductor devices (chips), or housings which constitute the communication devices. To realize such High-speed interconnection, a high-speed serial transmission technique has been used, which has increased the transmission rate per channel in a communication LSI (Large Scale Integrated circuit) to the order of multi-gigabit.
In general, as a communication LSI for such high-speed serial transmission, a circuit called a CDR (Clock Data Recovery) circuit for recovering a clock signal is used for recovery.
In order to recovery clock data, it is necessary to extract a clock synchronized with the data from reception data and re-time the data. For this reason, it is necessary to prepare a multi-phase clock with different phases in the CDR circuit in advance. Conventionally, such a multi-phase clock signal is generated by using a PLL (Phase Locked Loop) circuit.
FIG. 12 shows a schematic arrangement of a PLL circuit. A PLL circuit 101 is fundamentally comprised of a reference clock signal 104, a phase comparison circuit 107 for receiving frequency division outputs from a 1/N frequency divider circuit 105 and comparing their phases with each other, and a VCO (Voltage Controlled Oscillator) 110 for changing the frequency of an output signal 109 to the 1/N frequency divider circuit 105 in accordance with a comparison result 108 from the phase comparison circuit 107. When the phase difference represented by the comparison result 108 from the phase comparison circuit 107 is eliminated, the frequency becomes stabilized and N times the frequency of the reference clock signal 104.
A multi-phase clock signal 112 output from the PLL circuit 101 is supplied to a clock recovery circuit 113.
Some communication LSI for high-speed transmission is designed to switch transmission rates for serial data in accordance with the transmission distance or the state of an apparatus to which the LSI is applied. For example, the operation frequency of a high-speed serial data transmission circuit is switched over a wide range, e.g., to 625 MHz (megahertz), 1.25 GHz (gigahertz), and 2.5 GHz. In order to cope with such various kinds of required transmission rates, the oscillation frequency of the voltage controlled oscillator 110 must be changed in accordance with a change in the operation frequency of the multi-phase clock signal 112.
In this case, if the operation frequency of the multi-phase clock signal 112 changes in a wide range at ultra-high speed as in the above case, it is very difficult to design the PLL circuit 101, and more specifically, the voltage controlled oscillator 110, so as to obtain stable performance.
FIG. 13 shows a schematic arrangement of a multi-phase clock generation circuit that is proposed to solve such a problem. The same reference numerals as in FIG. 12 denote the same parts in FIG. 13, and a description thereof will be omitted as appropriate. A proposed multi-phase clock generation circuit 121 inputs an output 123 from the PLL circuit 101 in FIG. 12 to a multi-phase clock frequency divider circuit 124 to frequency-divide the output so as to generate a multi-phase clock signal 125. The multi-phase clock generation circuit 121 then supplies this signal to the clock recovery circuit 113.
The proposed multi-phase clock generation circuit 121 oscillates the voltage controlled oscillator 110 at a predetermined frequency, and obtains the multi-phase clock signal 125 after frequency division using the externally mounted multi-phase clock frequency divider circuit 124.
FIG. 14 shows the first example conventionally proposed as the multi-phase clock frequency divider circuit shown in FIG. 13. A multi-phase clock generation circuit 141 disclosed in Japanese Patent Laid-Open No. 2001-318731 includes first-phase to eighth-phase 8-phase clock output terminals 1421 to 1428 and a series circuit of first to eighth D flip-flop circuits 1431 to 1438 corresponding to the output terminals.
An 8-times clock generation circuit 144 supplies an 8-times clock signal 145 to clock input terminals CK of the first to eighth D flip-flop circuits 1431 to 1438. The 8-times clock signal 145 is obtained by multiplying the frequencies of clock signals output from the first-phase to eighth-phase 8-phase clock output terminals 1421 to 1428 by 8.
The 8-times clock signal 145 is input to a ⅛ frequency divider circuit 146, from which a clock signal 147 with the original frequency is output.
The clock signal 147 is input to an input terminal D of the first D flip-flop circuit 1431 located on the first stage of the series circuit described above. A first clock signal 1491 is output from an output terminal Q of the first D flip-flop circuit 1431 to the first-phase clock output terminal 1421. This signal is also input to an input terminal D of the second D flip-flop circuit 1432.
Likewise, subsequently, an nth clock signal 149n is generally output from an output terminal Q of an nth D flip-flop circuit 143n to an nth-phase clock output terminal 142n. This signal is also input to an imputer terminal D of an (n+1)th D flip-flop circuit 143n+1.
In the multi-phase clock generation circuit 141, the first to seventh D flip-flop circuits 1431 to 1437 shift clock signals from each other by one clock and supply the resultant signals to the D flip-flop circuits 1432 to 1438 on the next stages. As a result, first to eighth clock signals 1491 to 1498, which have a desired frequency and are 45° out of phase with each other, are obtained from the first-phase to eighth-phase 8-phase clock output terminals 1421 to 1428.
This proposed multi-phase clock generation circuit, however, requires the 8-times clock generation circuit 144 or generally the n-times clock generation circuit 144. As described above, the frequencies of clock signals have been extremely speeded up. In such a situation, it is very difficult to further increase the frequency by n times.
FIG. 15 shows another multi-phase clock frequency divider circuit that has been proposed to solve such a problem. The same reference numerals as in FIG. 14 denote the same parts in FIG. 15, and a description thereof will be omitted as appropriate. A multi-phase clock generation circuit 161 disclosed in Japanese Patent Laid-Open No. 2001-318731 inputs a reference clock signal 163 output from a reference clock generation circuit 162 to a 2-times multiplier circuit 164 to generate a clock signal 165 with a doubled frequency.
The reference clock signal 163 is a signal having the same frequency as that of signals finally obtained from first-phase to eighth-phase 8-phase clock output terminals 1421 to 1428. The clock signal 165 output from the 2-times multiplier circuit 164 is input to an n/4-phase clock circuit 166. The value n of the n/4-phase clock circuit 166 represents the number of phases. In this case, since 8-phase clock signals 1491 to 1498 are generated, the value n is 8. This circuit serves as a 2-phase clock circuit.
The 2-phase clock circuit 166 generates first and second clocks 167 and 168 having a total of two phases. The second clock 168 is output with a delay time, with respect to the first clock 167, which is equal to the period (corresponding to 45°) between the phases of the 8-phase clock signals 1491 to 1498 when they are output.
The signal state of the first clock 167 is inverted by a first inverter 169, from which a third clock 172 is supplied as an output to clock input terminals CK of third and seventh D flip-flop circuits 1433 and 1437. The signal state of the second clock 168 is inverted by a second inverter 170, from which a fourth clock 173 is supplied as an output to clock input terminals CK of fourth and eighth D flip-flop circuits 1434 and 1438.
The first clock 167 before inversion is supplied to clock input terminals CK of first and fifth D flip-flop circuits 1431 and 1435. The second clock 168 before inversion is supplied to clock input terminals CK of second and sixth D flip-flop circuits 1432 and 1436. The second clock 168 is further input to a ½ frequency divider circuit 175 to be frequency-divided by 2. An output 176 from the ½ frequency divider circuit 175 is supplied to an input terminal D of the first D flip-flop circuit 1431. The first to eighth D flip-flop circuits 1431 to 1438 are connected in series as in the case of the multi-phase clock generation circuit 141 in FIG. 14. The first to eighth clock signals 1491 to 1498 are respectively obtained from output terminals Q of the first to eighth D flip-flop circuits 1431 to 1438.
The multi-phase clock generation circuit 161 shown in FIG. 15 exemplifies the circuit arrangement for a case wherein the value n of the n/4-phase clock circuit 166 is “8” (8 phases). The following problems are posed in these conventional techniques.
One of the problems is that a single circuit cannot output multi-phase clocks with different frequency division numbers. This is because multi-phase clocks are generated by using a shift register. Assume that a shift register is used in the multi-phase clock generation circuit 141 shown in FIG. 14. In the case of n-phase clocks, clocks obtained by 1/n frequency division using a 1/n frequency divider circuit must be supplied to the shift register.
In the multi-phase clock generation circuit 161 shown in FIG. 15, in the case of n-phase clocks, an n/4-phase clock generation circuit and ½ frequency divider circuit are required. Therefore, a single circuit cannot output multi-phase clocks while arbitrarily switching frequency division numbers, e.g., 2, 4, and 8.
FIG. 16 shows a multi-phase clock generation circuit designed on the basis of the proposal shown in FIG. 15 to generate multi-phase clocks while switching the frequency division numbers 2, 4, and 8.
In a multi-phase clock generation circuit 181, a reference clock generation circuit 162 represented by a PLL circuit in the multi-phase clock generation circuit 161 shown in FIG. 15 is prepared, and reference clock signals output from the circuit 162 are input to a ½ frequency divider circuit portion 182, ¼ frequency divider circuit portion 183, and ⅛ frequency divider circuit portion 184 on the subsequent stage.
The ½ frequency divider circuit portion 182 includes a ½ frequency divider circuit 1802A, a 2-times multiplier circuit 1802B, and the remaining circuit shown in FIG. 15 or a corresponding circuit. The ¼ frequency divider circuit portion 183 includes a ¼ frequency divider circuit 1804A, a 2-times multiplier circuit 1804B, and the remaining circuit shown in FIG. 15 or a corresponding circuit. The ⅛ frequency divider circuit portion 184 includes a ⅛ frequency divider circuit 1808A, a 2-times multiplier circuit 1808B, and the remaining circuit shown in FIG. 15 or a corresponding circuit.
The ½ frequency divider circuit portion 182, ¼ frequency divider circuit portion 183, and ⅛ frequency divider circuit portion 184 respectively output a ½ frequency-divided multi-phase clock signal 185, ¼ frequency-divided multi-phase clock signal 186, and ⅛ frequency-divided multi-phase clock signal 187 to a selector 188. A phase count selection signal 189 is supplied to the selector 188. The selector 188 then selects and outputs a multi-phase clock signal 190 corresponding to a desired frequency division number.
As described above, in order to select one of multi-phase clocks with different frequency division numbers in the multi-phase clock generation circuit 161 shown in FIG. 15, for example, the circuit arrangement shown in FIG. 16 is required, resulting in an increase in circuit size.